1. Field of the Invention
The present invention relates principally to an information processing apparatus consisting of a plurality of nodes, each having at least a processor and a memory, and a connection line for connecting the nodes.
2. Related Background Art
For connecting a plurality of information processing apparatus (each of which will be called as a node in the present application), each of which has at least one processor and one memory for the purpose of data exchange between nodes, there are a method to connect them using one of various types of LANs and a method to connect them at address level of memory without using a LAN.
In these cases, an arbiter is generally provided for avoiding a conflict of access to a connection line between nodes and performing arbitration of a right of use of the connection line. Receiving connection line setting information from the arbiter, two nodes set up a connection line based on the information and exchange address information and the like through the set line, thereafter performing actual data transmission. FIG. 1 shows an example of the system for performing such an operation and FIG. 2 shows a timing chart to show a flow of the processing in that case.
In FIG. 1, reference numerals 100, 200, and 300 designate nodes, which are connected by a connection line 10. Each node includes a CPU 101, 201, 301, a memory 102, 202, 302, an interface circuit 103, 203, 303 for connection between the connection line 10 and the inside of each node, an arbitration interface circuit 104, 204, 304 used in requesting use of the connection line 10, and an internal bus 105, 205, 305 for interconnection between the listed internal components in node. Numeral 20 denotes an arbiter for performing arbitration of use of the connection line 10. The arbiter 20 is connected with each node by an arbitration signal line 110, 210, 310. Inside the arbiter there is a line selection information managing apparatus 21 for managing line request information sent from each node.
FIG. 2 shows an example where CPU 101 on node 100 reads data in memory 202 on node 200. In the timing chart as shown in FIG. 2, the horizontal axis represents lapse of time, an arrow a flow of signal and control, a rectangle a process executed in each processing apparatus, and a hexagon a state in which a variety of information is present for transmission on the internal bus, the connection line, or the arbitration signal line. Phases in the processing will be described one by one.
Phase 1
CPU 101 on node 100 issues an address on the common bus 105. Detecting it, the arbiter interface 104 notifies the arbiter 20 of the request for use of the connection line 10 through the signal line 110.
Phase 2
The arbiter 20 compares the request from node 100 with current circumstances of use of the connection line stored in the line selection information managing apparatus 21 and with circumstances of node 200 as a destination to be connected with, and notifies the node 200 of the connection request through the signal line 210 when it determines that they can be connected with each other.
Phase 3
Receiving the connection request from the arbiter 20, the node 200 immediately secures a circuit in the connection line interface 203 to the connection line 10. After completion of bus processing inside the node and when it becomes ready to receive a request from an external node, the node 200 sends a response of authorization of connection through the signal line 210 to the arbiter 20. Receiving the response, the arbiter 20 informs the node 100 of the authorization of line setting through the line 110. The arbiter interface 104 in node 100 gives an instruction of line setting to the connection line interface 103, based on the received information.
Phase 4
The node 100 sends an address of requested data from the connection line interface 103, onto the line 10. Based on the received address from node 100, the node 200 accesses the memory 202 through the internal bus 205.
Phase 5
The node 200 sends data supplied from memory 202 through the connection line interface 203 onto the connection line 10, and the node 100 receives it through the connection line interface 103. The received data is provided to CPU 101 through the internal bus 105 in node 100.
As described above, the data transfer was executed by successively processing the above phases.
However, where the data transfer is executed by successively processing the phases as shown in FIG. 2, i.e., in the case where the connection line is first set up, then the address information or the like is exchanged through the set line, and thereafter actual data transfer is carried out, overhead required for setting up the transmission line and for transmission of additional information (for example, such as address) to carry out data transfer is inevitable in addition to a time necessary for actual exchange of data, resulting in a problem of a decrease in efficiency of actual data transfer. In particular, where the time due to the overhead was long, or where the data transfer speeds on the line between nodes was slower than the processing speeds of the bus and other components in the each node, the actual data transfer efficiency was greatly lowered.